Financial ABV : Accredited in Business Valuation (ABV) Exam

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Exam Number : ABV
Exam Name : Accredited in Business Valuation (ABV)
Vendor Name : Financial
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ABV test Format | ABV Course Contents | ABV Course Outline | ABV test Syllabus | ABV test Objectives

The Accredited in Business Valuation (ABV ®) credential is granted exclusively by the AICPA to CPAs and qualified valuation professionals who demonstrate considerable expertise in valuation through their knowledge, skill, experience and adherence to professional standards. To obtain the credential, you must pass the two-part, modular ABV Exam. The test requirement is waived for candidates who have passed the ASA credential test of the American Society of Appraisers, CFA test level III of the CFA Institute or CBV credential test of the Canadian Institute of Chartered Business Valuators.

The AICPAs ABV credential is the most rigorous and prestigious of the business valuation certifications. In a short time, it has become an essential marketing tool for the CPA planning to specialize in this lucrative practice area.

Review sources of data, techniques, and methods used to analyze business interest, value drivers, and risk assessment.
Distinguish among the three primary approaches to value (and related hybrid approaches), as well as identify and apply various types of valuation adjustments and the reconciliation of value estimates.
Identify key areas related to valuation in the conceptual framework of fair value accounting, accounting for business combinations, and accounting for goodwill impairment.
Identify the five basic steps of a valuation engagement.
Differentiate among standards of value, premises of value, and levels of value.
Identify valuation related professional standards and guidelines issued by AICPA (for example, VS section 100).

Newly enhanced and closely aligned with the ABV exam, the AICPAs ABV test Review is the only comprehensive BV examination review program backed by the resources and collective expertise of business valuation professionals associated with the nation's premier membership organization for CPAs.

The AICPAs ABV credential is the most rigorous and prestigious of the business valuation certifications. In a short time, it has become an essential marketing tool for the CPA planning to specialize in this lucrative practice area. A key step towards becoming an ABV, the ABV test tests a comprehensive range of business valuation knowledge.

The ABV test is offered in a two-part, modular format. Module 1, "Approaches", covers Content Specification Outline (CSO) section II and chapters 4-7 and 9 of ABV test Review. Module 2, "Analysis and Related" covers CSO sections I & III and chapters 1-3 and 8 of ABV test Review. Please reference the CSO before preparing for the ABV exam.

NOTE: Taking this review course does not ensure that the candidate will successfully pass the ABV exam. This course reviews most of the items on the exams content specific outline and is not meant to teach Topics to the candidate for the first time. A significant amount of independent studying and study will be necessary to prepare for the exam, regardless of whether or not the candidate completes this review course.

Key topics:
Professional Standards, the Engagement, and Standards of Value
Fair Value for Financial Reporting Based on Financial Accounting
Standards Board Accounting Standards Codification (FASB ASC) 820
Subject Company Analysis
Income Approach to Value
Cost of Capital
The Market Approach to Valuation
Asset-Based Approach
The Valuation of Intangible Assets and Intellectual Property
Valuation Adjustments: Discounts and Premiums and Reconciliation of Indicated Values

I. Foundation of Valuation Theory (Exam Part 1 — 50%)
A. Professional standards
B. Financial reporting
C. Defining the engagement
D. Sources of economic and industry data
E. Macro-economic and environmental analysis
F. Industry analysis
G. Subject entity analysis
II. Implementation of Valuation Methods (Exam Part 2 — 50%)
A. Valuation approaches
B. Intellectual property and other intangible assets
C. Discounts, premiums and other adjustments
D. Conclusion of value
A. Professional standards
1. AICPA VS Section 100, Valuation of a Business, Business Ownership
Interest, Security, or Intangible Asset (VS Section 100)
2. AICPA Code Of Professional Conduct ET 1.200.001 “Independence
rule” and interpretations of the “nonattest services” subtopic [1.295]
(Pronouncements and regulations related to independence
requirements when providing business valuation services to attest clients)
Understanding Business Valuation: A Practical
Guide to Valuing Small to Medium-Sized
Businesses, chapter 2
Financial Valuation: Applications and Models, chapter 12
B. Financial Reporting
1. Fair value measurements (FASB ASC 820)
2. Business combinations (FASB ASC 805)
3. Goodwill and other intangibles and measuring impairment
(FASB ASC 350)
4. Accounting for the impairment of long-lived assets (FASB ASC 360)
5 Compensation — stock compensation (FASB ASC 718)
6. Contingent considerations
7. AICPA Statement on Auditing Standards AU Sec. 336 (Using the Work
of a Specialist) And AU Sec. 328 (Auditing Fair Value Measurements
And Disclosures)
Understanding Business Valuation: A Practical
Guide to Valuing Small to Medium-Sized
Businesses, chapter 19
Financial Valuation: Applications
and Models, chapter 24
C. Defining the engagement
1. Standards of value (e.g., fair market value, fair value — financial
reporting, investment value, intrinsic [fundamental] value)
a. Internal Revenue Service (IRS) Revenue Ruling 59–60 (fundamental
valuation considerations and the definition of fair market value)
2. Relationship between purpose of the valuation and the standard of value
3. Understanding the ownership characteristics of the interest being valued
4. Premise of value for business interests (i.e., ongoing concern and liquidation)
5. Engagement letters (e.g., purpose and content)
Understanding Business Valuation: A Practical
Guide to Valuing Small to Medium-Sized
Businesses, chapters 3, 4 and 16
Financial Valuation: Applications
and Models, chapter 2
VS Section 100
D. Sources of economic and industry data
E. Macro-economic and environmental alalysis
F. Industry analysis
1. Industry structure and life-cycle analysis
2. Competitive strategies and analysis
G. Subject entity analysis
1. Entity documents (e.g., operating agreements, buy-sell agreements and bylaws)
2. SWOT (strengths, weaknesses, opportunities and threats) analysis
3. Firm economics (cost structure and pricing power marginal analysis)
4. Historic and forecast financial statements
a. Common size
b. Trend analysis
c. Financial ratios (a list of definitions, ratios and formulas provided during the test is included at the end of this document)
d. DuPont analysis; return on equity and return on assets
5. Adjustments to historic and forecast financial statements
a. Normalizing
b. Control vs. non-control
c. Separation of operating and non-operating items
d. Off balance sheet items
1) Other adjustments
2) Implied tax adjustments
3) Inusual and/or non-recurring items
4) GAAP based adjustments
Section II. Implementation of Valuation Methods (Exam Part 2 — 50%)
This section covers knowledge of the three primary approaches to value; intellectual property and intangible assets; levels of value; discounts; premiums and the conclusion of value.
A. Valuation approaches
1. Income approach
a. General theory
b. Sources of data
c. Commonly used methods
1) Capitalized economic income/cash flow method (CCF), including Gordon Growth Model (consistent growth model)
2) Discounted economic income/cash flow method (DCF), including Gordon Growth Model (two-stage model)
3) Excess earnings method (hybrid method)
d. Commonly used models — direct equity model versus invested capital model
e. Types of benefit streams and selection
f. Cost of capital concepts and methodology and other models
1) Capital asset pricing model (CAPM) and beta (B) including unlevering and relevering betas
2) Build-up method
3) Duff and Phelps risk premiums
4) Weighted average cost of capital
5) Understanding the security market
6) Understanding option pricing theory
g. Selection of appropriate time (including mid-year convention)
2. Market approach
a. General theory
b. Sources of data
c. Commonly used methods
1) Transactions in subject companys stock
2) Guideline publicly traded company method
3) Guideline merged and acquired company (transaction) method
d. Selecting guideline companies
e. Statistics related to valuation analysis
1) Understanding measures of central tendency (e.g., Arithmetic, harmonic and geometric means and median)
2) Understanding measures of dispersion (e.g., Variance and standard deviation)
3) Understanding statistical strengths of numerical relationships (including covariance, correlation, coefficient of determination and coefficient of variation)
4) Understanding linear regression
f. Equity versus invested capital (including price multiples)
g. Selection of appropriate time periods
h. Selection and adjustment of appropriate multiples
Understanding Business Valuation: A Practical
Guide to Valuing Small to Medium-Sized
Businesses, chapters 9 and 10
Financial Valuation: Applications and Models, chapter 8
3. Asset approach
a. General theory
b. Sources of data
c. Adjusted (net) asset method
d. Considerations in liquidation
e. Issues in valuing intangible assets
f. Tax affecting the balance sheet
B. Intellectual property and other intangible assets
1. Valuation approaches and methods
2. Valuing specific intangible assets
Understanding Business Valuation: A Practical
Guide to Valuing Small to Medium-Sized
Businesses, chapter 20
Financial Valuation: Applications
and Models, chapter 24
C. Discounts, premiums and other adjustments
1. Levels of value appropriate to the engagement
a. Control strategic (public or private company)
b. Minority/control standalone liquid (public company)
c. Control liquid (private company)
d. Control standalone (private company)
e. Minority non-marketable (private company)
2. Discount for lack of control (DLOC) and control premium
a. Sources of data
b. Ownership characteristics
c. Magnitude
3. Discount for lack of marketability (DLOM)
a. Sources of data
b. Ownership characteristics
c. Restrictions and transferability
d. Magnitude
4. Discount and premiums — understanding the empirical studies
5. Allocation between voting and non-voting stock
6. Other valuation discounts and adjustments
a. Market absorption and blockage discounts
b. Key person/thin management discounts
c. Built-in gains tax discount
d. Nonvoting stock discount
Understanding Business Valuation: A Practical
Guide to Valuing Small to Medium-Sized
Businesses, chapters 14 and 15
Financial Valuation: Applications
and Models, chapter 10
D. Conclusion of value
1. Reconciliation of indicated values
2. Reasonableness of conclusion

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Financial (ABV) test

Introduction to SVA Assertions for Design Engineers | ABV test Questions and test Cram

by way of Eric Deal of Cyclic Design, LLC

Assertions and statement-based Verification (ABV) are a sizzling topic, but many engineering groups continue to be unfamiliar with the benefits that assertions convey to the design and verification system. This paper discusses the purpose for the use of assertions, the advantages of using assertions all over the design and verification system, and a step-with the aid of-step method to implementing assertions inside a design.

This whitepaper is written from the perspective of a design engineer. expectantly each design and verification engineers will see the relevance of (and humor in) these feedback from the designercentric world view.

Assertions in the Design system

implementing assertions within a design requires a aware choice on the a part of the designer to view the design process in a different way. typically, designers method a design in 4 tiers:

  • benefit an understanding of the necessities of the design/algorithm,
  • Design RTL to implement an answer,
  • function some elementary testing to verify fundamental performance.
  • Debug examine disasters found with the aid of verification engineer
  • There can be variations to the method, akin to creating a micro-architectural specification, but these additional steps often fall into one of the most above classes. adding assertions, although, requires an further step, which likely explains why designers haven't with ease adopted statement use.

  • profit an figuring out of the requirements of the design/algorithm,
  • Design RTL to enforce an answer,
  • Add SystemVerilog Assertions (SVA)
  • function some fundamental testing to verify primary functionality.
  • Debug look at various screw ups found through verification engineer
  • As designers start to keep in mind the vigor of assertions, they're going to effortlessly undertake them if for no other motive that pure selfishness: spending time creating assertions minimizes time spent debugging later.

    merits of Assertions

    Assertions incorporated right into a design advantage each the design and verification engineer. an awful lot of a fashion designer's time is in reality spent debugging problems present in the design all over the verification process. usual considerations that come up all the way through verification (specially for restricted-random trying out) include:

  • common sense bugs within the design
  • Inaccurate behavioral models in response to poorly documented interfaces
  • Invalid programming or use models
  • while we (as designers) respect the work being executed through the verification engineers to verify our designs, we also secretly dread the sight of them in our doorway, in view that that often capability whatever failed that we now deserve to debug. during this case, we ought to either interrupt our existing work or put off debugging the testcase unless we get to a great stopping aspect. both situations outcome in an interruption of the verification engineer's work, however i believe many verification engineers dread the latter situation, since it regularly ability they ought to interrupt work on testbench building growth to ensure the failing case will also be reliably recreated.

    in many cases, assertions permit us to destroy this cycle. They essentially act as pink flags all over simulation pinpointing failures that may either at once cause check screw ups or now not be detected by means of passing exams.

    Assertions on module interfaces can directly establish invalid conduct that may be led to by way of a behavioral model or incorrect use of the design (invalid register settings, invalid operating modes, and so forth). Such assertion screw ups point out that a problem could be with the testbench, enabling the verification engineer no longer only to pinpoint the cause of the failure, however also to at once update the testbench and continue with verification, often with out even having to consult the design engineer. In situations the place the design is at fault, the design and verification engineers can immediately get to the bottom of the concern without extensive debug, as a result of they understand where and when the failure took place.

    inside design assertions additionally support locate the root reason for failures that directly outcomes in testcase disasters. for instance, constrained-random testbenches frequently discover nook instances comparable to FIFO overflow/underflow circumstances which are consistently now not exercised with the aid of directed checks. Debugging failures comparable to these takes time given that the clothier has to hint again the failure at the conclusion of a examine (which may also conveniently be invalid information in equipment memory) to the foundation explanation for the failure. including even a couple of elementary assertions on interior FIFOs or interfaces will often locate these screw ups on the time and element of failure, eliminating the need for a lengthy debug session.

    ultimately, assertions increase reuse considering that they seize design intent that may be misplaced as design and verification engineers well-known with the design circulate to new initiatives. a few of this information may be captured in micro-structure documents, however who in fact reads the manuals except there's an issue? With assertions latest, it's far more likely that problems integrating reusable good judgment could be discovered.

    finally, designers like to create issues. As design engineers begin to be aware how assertions reduce debug time and energy, they are going to know that time spent growing assertions pales in assessment. Some designers may even come to view adding assertions as a creative challenge.

    a different mind-set

    including assertions requires the fashion designer to think of the design from a different element of view. instead of viewing alerts as the implementation of an answer, designers have to step again and think about what rules the design, bus/signal protocols, or usage model impose on these indicators. These rules must then be coded in an fact language such because the SystemVerilog fact language (SVA), to be able to seize the conduct of particular person signals or the interplay of a couple of linked alerts.

    it is critical to note that assertions may still not without problems recreate suggestions forced on signals by using a selected implementation. as an instance, coding an statement to recreate the transitions in a state desktop is probably now not terribly beneficial. despite the fact, coding assertions relating events happening at a module's interface to the habits of a state computer may also be very effective.

    in order to focus on the technique of developing assertions, this paper will center of attention on developing a simple subset of assertions for ARM's AXI bus interface. In doing this, we simplify the assertion writing procedure considering assertions might be written for a well-recognized protocol, and we are able to use the AXI specification as our record of necessities.

    growing Assertions

    Step 1: establish target Modules and alerts

    step one when including assertions is to identify the module or community of alerts the place assertions may still be utilized. commonly it's less demanding to describe the habits of manage indicators than records indicators since algorithmic operations don't lend themselves to standard behavioral guidelines. control signals, although, frequently are responsible for responding to external and inside stimulus, and for that reason, their behavior and interplay is more quite simply described. For our AXI illustration, we are able to determine the complete set of AXI alerts as our target, but for more common purposes, designers might also decide to center of attention more time including assertions at interface boundaries or modules with excessive stages of control common sense.

    including assertions at the boundary of a module provides an extra improvement. in addition to checking that the internal good judgment is compliant, they determine that the external atmosphere behaves in keeping with these rules. These assertions can for this reason check for invalid testbench configurations or protocol violations as well as issues in different blocks that could later be interfaced to this module.

    Step 2: Create suggestions through Paraphrasing Intent

    Many engineers are overwhelmed by the possibility of adding assertions, principally since it takes time to suppose of a rule and then code the associated assertion. constantly switching between the correct-mind endeavor (exploring associations) and left-mind exercise (synthesizing the associated SVA assemble) makes the system look very disjointed.

    a higher method is to break up the procedure into two separate steps. First brainstorm as many rules as possible, and simply write every as a phrase lots like an RTL remark. Later, take all these phrases and code them as SVAs. by way of doing this, you're going to locate that you should create a richer set of assertions while streamlining the procedural points of coding the assertions.

    For our AXI instance, we might brainstorm right here guidelines for the write tackle bus (these are only a couple of):

  • AWBURST can also in no way be 2'b11 (reserved)
  • AWCACHE need to not ever be 4'b010x, 4'b100x, or four'b110x
  • When AWVALID goes excessive, it have to remain high unless AWREADY is asserted
  • When AWVALID goes high, AWADDR/identification/LEN/size/and so on must stay reliable until AWREADY
  • When an tackle is authorized (AWVALID & AWREADY) we need to see a corresponding response with the same identity (BVALID & BREADY) at some element later in time
  • every of the channels shares some of these rules, so many can be reused when growing assertions for the other AXI indicators. a lot of these guidelines come at once from the AXI specification – all an engineer must do is read the specification and search for phrases that can be interpreted as guidelines.

    Step three: Code SVA Assertions

    Now that we now have an inventory of guidelines, we can swap over to our left-mind to code the SVA statements.

    this is made much more convenient when you consider that we have already got an outline of the guideline and simply should find the premier method to categorical the rule of thumb in the SVA language. At this point, engineers have a call to make: they could both code within the SVA with the aid of hand or use a third-birthday party device similar to Zazz to automate the project. Coding without delay in SVA, the assertions from step 2 are as follows (just the SVA sequences are proven):

  • AWVALID & AWREADY |-> (AWBURST!=2'b11)
  • AWVALID & AWREADY |-> (AWCACHE[3:1]!=3'b010) & (AWCACHE[3:1]!=3'b100) & (AWCACHE[3:1]!=3'b110)
  • The final assertion (not proven above) is extra advanced and would probably take a person skilled in SVA to code it. besides the fact that children, all of those assertions are trivial to code the use of Zazz:

    AWBURST and AWCACHE checking (mixed)

    AWVALID high unless AWREADY and stable controls (mixed)

    Full determine of handle write via facts switch and write response*

    the full SVA sequence (created through Zazz) is relatively intimidating:

    Step four: Debug Assertions

    Assertions are only like some other good judgment assemble, so it's crucial that the assertions are coded to accurately describe design conduct; otherwise, both design and verification time could be spent debugging false fact screw ups, negating the benefit of the usage of assertions within the first region.

    traditionally, assertions are debugged by means of working dynamic simulations or using formal equipment to activity the good judgment and assertions. screw ups in the design and assertions are then iteratively corrected as verification proceeds. often basic assertions require little debug when you consider that the rules they carry are pretty absolute. as an example, the fact “AWVALID should be de-asserted right through reset” (~ARESETn |-> ~AWVALID) is pretty problematic to code incorrectly.

    more complicated assertions present a special situation. regularly when coding an fact that describes the interaction between two or more alerts, the designer envisions a waveform that describes this conduct after which codes an SVA to explain these relationships. The difficulty is that the SVA is a temporal modeling language, which is inherently distinctive from modeling digital common sense*. This regularly ends up in issues where the fashion designer's intent within the coded SVA does not match the genuine behavior of the assertion.

    The issue is that a dressmaker must close the loop between fact intent (the intellectual graphic of a waveform) and the actual habits of the assertion (the coded SVA). Zazz addresses this problem with the aid of generating a small randomized testbench around each and every individual fact, permitting the fashion designer to instantly examine behaviors associated with the assertion, for that reason closing the loop between intent and habits. As an additional benefit, this method frequently leads designers to see additional relationships which should be described to extra thoroughly constrain conduct, resulting in even better best assertions.

    as an example, let's code the statement “AWVALID have to remain asserted except AWREADY and AWLEN need to stay stable all over this time.” The designer could envision intent as shown within the sketch beneath:

    using Zazz to construct the statement, it could appear to be the diagram under*. It says that when AWVALID is asserted, the assertion should wait until AWREADY is asserted, after which follow two constraints all the way through this time: AWVALID have to remain real and AWLEN ought to remain reliable (the different control indicators are ignored for simplicity).

    the use of the SVA Debug feature, Zazz generates some stimulus and enables the engineer to peer how the statement behaves, as proven within the photo under:

    We see that the statement is failing on a number of scenarios. The problem is that the $sturdy on AWLEN may still no longer apply on the first cycle but in its place, simplest on subsequent cycles. It additionally suggests that the statement triggers assorted attempts on the identical event (which may now not be the desired habits for some assertions).

    The corrected assertion and its linked waveform are shown below:

    This edition units a short lived variable (awlen) to dangle AWLEN after which expects the AWLEN field to healthy this cost until AWREADY is asserted (both instantly or on some subsequent cycle). moreover, the fact assessments that AWVALID is still authentic right through this time duration. The resulting waveform not shows the assertion disasters and the pattern waveforms match the customary intent. (observe: this verify may still be extended to check AWLEN, AWSIZE, ... in its place of simply AWLEN).


    whereas assertions may also be a magnificent addition to a design group's arsenal, they force designers to spend time early in the design system adding first-rate assertions. Design engineers may also withstand adding assertions as a result of tight time constraints and the complexity of the SVA language. inspite of the time discounts for designers all over the verification technique, including assertions to the design technique has remained a tough sell.

    equipment equivalent to Zazz increase ease-of-use to the factor that designers can now with ease contain assertions into designs. The inclusion of splendid assertions all the way through the design will reduce not best the time spent debugging designs, but also the time spent communicating considerations between the design and verification engineers. These identical assertions may additionally also realize “hidden” screw ups that don't propagate to an observable aspect that results in testcase failure, increasing the chances of finding such issues before tapeout.

    The present attitude that assertions belong simplest in the verification system needs to trade. As designers start to take into account that assertions are handy to comprise early in the design procedure, design groups can recognize the advantages of assertions during the complete design and verification manner. an internet version of this paper and video tutorial is obtainable at

    concerning the creator

    Eric Deal, President, Cyclic Design LLC  

    Eric has 18 years digital common sense design and structure event at IBM, Rockwell/Conexant, Sigmatel, Multixtor, and most recently along with his personal IP/consulting business, Cyclic Design, which makes a speciality of error correction for NAND flash. Eric has helped Boost a couple of SOC platforms and has event in clocking, bus connectivity, and building in ECC, encryption, safety, photo processing, and that i/O interfaces. He promoted using OVL assertions while at Conexant and became an early adopter of SystemVerilog assertions at Sigmatel. Eric has been a expert for Zocalo due to the fact that 2009, and was instrumental in setting up the chicken Dog algorithm and the visible SVA concept.


    Zocalo Tech, Inc., incorporated in 2006, is focused on productiveness software for short and simple creation, use and reuse of assertions that work with popular functional verification flows. Zocalo utility, marketed beneath the identify Zazz, has been architected and developed from the floor up with one intention in mind: expanded productivity for engineers adopting and using assertion-based Verification. For extra suggestions, please seek advice from

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