IBM C4030-670 : xSeries Sales V2 Exam

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Exam Number : C4030-670
Exam Name : xSeries Sales V2
Vendor Name : IBM
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IBM V2 testing

Embedded Symmetric MultiProcessing device on a SoC with 1.6GHz PowerPC IP in 45nm | C4030-670 real questions and Cheatsheet

by means of Gerard Boudon, IBM Microelectronics


since the dimensions of lithography are actually nearer to the primary genuine limits, scaling is further and further complex and accordingly multi-core processor solutions are only growing to be greater frequent in the embedded enviornment. This paper describes in particulars the facets that allow SoCs to be developed with up to eight 1.6 GHz PowerPC CPU cores in an embedded device supporting Symmetric Multiprocessing (SMP) structure. The balancing between CPU execution speed, memory bandwidth and latency, and coherency overhead has been the purpose of the design of the PLB6 and the L2 Cache IP's, to in the reduction of as a good deal as possible the drop-off in performance-per-core inherent in an SMP approach.

1. Introduction

In September 2009, [1] IBM has introduced an 1.6 GHz PowerPC CPU IP in 45nm SOI - 3.6mm2 size - that can be built-in in multi-core equipment-on-chip (SoC) product families for conversation, storage, consumer, and aerospace and defense embedded functions.

2. PowerPC476 IP

The PowerPC 476FP embedded processor core is a 5- subject, 5-pipeline, superscalar, 32-bit decreased instruction set computer (RISC) processor. The core supports the power instruction Set structure V2.05. The core additionally helps reminiscence coherency to expand ASIC options into multiprocessing gadget environments and to boost its scalability.

The universal company of the processor core is proven on determine 1 .

guide route

The PowerPC 476FP processor is a excessive performance core with skill to difficulty up to five-guidelines per cycle. These directions can feed in parallel right here five fixed factor gadgets as neatly because the separate floating-aspect (FP) pipeline:

  • department pipeline
  • Load and keep operations
  • primary arithmetic and logical operations
  • primary and complex guide pipeline,
  • Multiplication and division pipeline
  • L1 Cache

    The L1 32 KB guideline and L1 32 KB facts caches are two-cycle pipelined cache accesses, with index of true handle in the 1024-entry unified translation lookaside buffer (UTLB)

    The L1 Cache tackle and data Caches are snoopable. Early beginning of guidelines to the floating-factor unit is enabled because all guidelines are predecoded

    Floating-aspect Unit

    The floating-aspect unit (FPU) is a pipelined, doubleprecision math computation processing unit that's attached to the processor core. The FPU conforms to the IEEE usual for Binary Floating-element Arithmetic. The FPU is a Six-stage super-pipelined floating-factor arithmetic execution with unbiased floating-factor load-and-store and execution units

    determine 1: PowerPC476 CPU core block diagram

    vigour Saving

    The PPC476FP includes design aspects to lower the working power of the PowerPC 476FP

  • All latches are clock gated in order that idle capabilities do not waste energy.
  • All non executing and idle services are disabled.
  • Static random access reminiscence (SRAM) is partitioned so that only the necessary memory zone is enabled or chosen.
  • Doze and idle sleep modes can be found.
  • The crucial logic and the floating-factor unit have separate clock makes it possible for
  • three. L2 Cache

    The L2 Cache IP [2] will also be configured in 256K, 512KB or 1 MB with a maximum of four,096 entries. The L2 cache line is 128 byte and the cache is four means set associative. To guide the high RAS (Reliability and Serviceability) requirement of the networking software, the L2 Cache arrays are included by using Parity and ECC bits.

    IP size (bits) insurance plan L2 Cache four,096x128x8x4 ECC Cache Tag 4,096x36x4 ECC LRU 4,096x30 Parity

    desk 2 : SRAM array interior a 1MB L2 Cache IP.

    figure 2: SMP implementation with the PPC476 showing L2 Cache states

    4. PLB6

    The 476FP “subsystem” which includes the PowerPC 476FP CPU core, the stage 2 cache/cache controller, is linked to other “subsystems” in the course of the PLB6, the latest architectural extension of the CoreConnect native bus architecture. This constitution allows SoC designers to conveniently and unexpectedly strengthen entire households of products, scaling the number of “master” cores from 1 to 16 (together with 1 to eight Coherent CPU cores) on the bus. The PLB4 CoreConnect interior Bus is a shared bus of 128bit facts at a highest pace one fourth of the CPU pace. It become designed for sub 1GHz CPU cores. excessive efficiency is completed with a dual bus constitution one bus with a high throughput and the 2nd with low latency. each of them is independently in a position to coping with examine and write operations on the identical time.

    the new IBM CoreConnect PLB6 bus appears more like a material with high speed aspect to point hyperlinks, with each and every of them having 128 bit read and 128 bit Write facts paths at one half of the CPU clock pace.

    The bus cloth on the PLB6 is able to supporting as much as 8 coherent master features, giving SoC designers the flexibility to mix and suit I/O masters, processors and different accelerators inside the textile.

    The high throughput of this bus is because of its material constitution with up to eight slave segments, that can simultaneously receive or transmit records.

    each slave phase can also have as much as four slaves. it's possible, in 45nm technology and without any preplacement in silicon, to function the bus structure at up to 800MHz.

    figure three: master and Slave attachments to the PLB6 CoreConnect bus

    Symmetric Multiprocessing (SMP)

    as a way to guaranty coherency between facts in main reminiscence and information in the quite a few caches, the design of a traditional SMP system is following the MESI protocol:

  • M Modified
  • E exclusive
  • S Shared
  • I Invalid
  • These states are linked to every cache line (L2 for the PPC476). each CPU performs snooping operation where these cache states are used. notice that the cache within the SMP processors architecture must have the identical Cache line size and the identical MESI states.

    The efficiency of such coherent SMP equipment is limited by the proven fact that transactions are feasible most effective between the Cache and the main memory. for instance, when a CPU 1 wants to study a knowledge it truly is in a M (Modified)

    state in the cache of a CPU2, the primary operation is for the CPU2 to write down the facts within the memory, after which the CPU1 can read it. outcome; 2 operations with 2 memory access are needed for CPU1 to get the facts.

    With the symmetric multiprocessing structure, scaling up the number of processors, is effective if on the same time the hardware coherency is smart satisfactory to address the massive bandwidth demand of the coherence transactions.

    it's imperative to have a non-blocking off coherence resolution which prevents stopping CPU execution many of the time; in the PPC476 three further states are delivered in the L2 cache with a view to enable Cache to Cache transfer, and improved Atomic operations.

    The information switch is eased via a committed direction between distinct subunit known as Intervention records route. These three states are:

  • MU Modified Unsolicited
  • T Tagged
  • SL Shared last
  • Intervention

    The purpose of intervention through a CPU master is to reduce the latency obligatory to fetch a cache line when it isn't latest in its L2, however is present in different L2’s.

    The SL (Share remaining) state is used for Intervention. It designate one (simplest) cache accountable to provide the records after an intervention. As effect of an intervention among L2’s, Cache to Cache switch is achieved as an alternative of memory access after a L2 pass over.

    5. illustration of SoC implementation

    An illustration of device implementation is shown in determine four. The PLB6 is primarily reserved for prime pace entry and for dealing with reminiscence coherency due to using dissimilar CPU cores. The gadget memory is also attached to the PLB6 as a result of fast access to memory is very vital for operating code and provides information no longer already in cache. because of high speed of the CPU it is critical to deliver statistics from main memory at a speed that simplest the late generation of DDR3-1600MHz SDRAM may give.

    A SoC requires also high speed I/O’s, which are connected right here below a PLB6 to PLB4 interface. These I/O are often PCI specific with 2nd era 5gbps per port throughput. Legacy Ethernet is also mandatory since it is vital at least to load code within the system. other IP blocks such as USB or SATA will also be linked through an AXI bus for example.

    figure 4. instance of SoC in line with the PPC476 IP

    6. genuine implementation

    SOI: with a view to in the reduction of vigour and electrical leakage, the choice of 45nm silicon-on-insulator (SOI) know-how became made. SOI can supply as much as a 30 % chip performance improvement and 40 % vigour reduction, in comparison to general bulk silicon technology [3]. This know-how is used via IBM in a wide range of application-specific integrated circuits (ASIC) and foundry purchasers as well as in chips for its servers and storage items.

    For performance and vigour dissipation optimization, the PowerPC476FP CPU IP has been designed in a hard core, whereas for flexibility in personalization, L2 cache and PLB6 are synthesizable; see layout of the PPC476 core on figure 5. right here table indicates quite a few areas of the IP block necessary to construct an SMP device.

    IP sizePPC476 tough Core IP three.6 mm2 L2 Cache delicate IP 4mm2 * PLB6 cntl gentle IP 0.035mm2 **

    * 512 KB L2

    ** Masters 4 C + 1 - Slaves 1C + 2 (C=Coherent)

    table 2: Core size in 45nm SOI expertise.

    determine 5: PowerPC 476 CPU 3.6 mm2 tough core

    7. Design verification by using emulation

    functional verification of the PowerPC 476FP CPU, L2 cache and PLB6 bus advanced made huge use of hardware emulation through a customized multi-core FPGA primarily based verify board. besides tremendously dashing up the design verification effort, this emulation platform has offered for Linux kernel and device driver configuration and trying out, and it is presenting for extensive early code construction and benchmarking.

    8. Conclusions

    It has been agreed within the industry that the way forward for embedded system is multi core. The PPC476 comprises 3 key IP cores; the 1.6GHz CPU, the L2 cache and the PLB6, which mixed collectively, helps SoC designers to developed embedded system with the maximum efficiency. This performance is done with the coherence of data managed by hardware help.

    9. Acknowledgements

    thanks to the IBM PowerPC design team for proposing information used to put together this paper.


    [1] B. Talik “Introduction to the new high-performance IBM PowerPC 476FP Core” - Linley Tech Processor Conf Sept 17,09.

    [2] W. Nation “Multicore Processor Cache and Subsystem Design for a high-efficiency PowerPC concentrated on Networking and Storage” - Linley Tech Processor Conf Sept 17,09.

    [3] R.Pottier & al "ARM 1176 implementation in SOI 45nm technology and silicon measurement" IEEE foreign SoI conference Oct 2009

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