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Exam Name : Foundry Networks Certified Layer4-7 Professional
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Cadence Collaborates With common Platform and Arm to carry forty five-NM RTL-to-GDSII Reference circulation | FN0-240 PDF download and Latest Topics

Reference circulate uses CPF-Enabled Cadence Low-energy solution and Key DFM technologies for advanced Node Designs

SAN JOSE, CA-- Jun 9, 2008 -- Cadence Design systems, Inc. (NasdaqGS:CDNS - information), a pacesetter in international electronic design innovation, nowadays introduced the forty five-nanometer reference movement targeting regular Platform(TM) know-how accessible for well-known liberate in July 2008. Cadence® and the regular Platform know-how companies, comprised of IBM, Chartered Semiconductor Manufacturing and Samsung Electronics, collaborated to Excellerate this RTL to GDSII forty five-nanometer circulate to handle advanced node design requirements. This reference circulation is in line with the general vigour layout (CPF)-enabled Cadence Low-vigour solution and additionally includes key Design For Manufacturing (DFM) technology from Cadence. This joint optimization is anticipated to provide large power discount rates, yield enhancement and time-to-market merits for consumers designing excessive-extent client, communications and mobile electronic instruments targeted to the usual Platform technology 45-nanometer system.

This reference stream makes use of the 45-nanometer ARM® physical IP low-energy libraries and makes it possible for designers to operate design exploration and physical prototyping the use of distinctive CPF data and a single golden RTL, permitting low-energy structure optimization. It employs the superior vigor management capabilities within the Cadence Low-vigor answer -- including power shut off prototyping, power area-aware placement, clock tree synthesis and routing, multi-mode and multi-corner evaluation and optimization -- to convey higher productivity and the utmost in power reduction for advanced designs.

"buyer demand for portable items is accelerating as longer, respectable connectivity turns into a necessity. here's using an increasing demand for designs with optimized vigor administration schemes," pointed out Tom Lantzsch, vp of advertising and marketing, genuine IP Division at ARM. "Working with Cadence, ARM is aggressively pursuing the enablement of our mutual purchasers to Excellerate industry main embedded items. As part of this collaboration, we at the moment are offering CPF views with the ARM genuine IP libraries. The 45-nm ARM physical IP with power management kit focused to the average Platform expertise is the latest evolution of our commitment to CPF-based mostly reference flow collaboration with Cadence."

As part of this 45-nm reference stream, Cadence additionally provides an built-in suite of foundry certified, mannequin-primarily based DFM evaluation and implementation applied sciences for silicon-accurate analysis and genuine design optimization. These applied sciences present silicon-accurate modeling and optimization of vital manufacturing variations that can be used to enrich each performance and physical yield outcomes all through design implementation. At superior procedure nodes, average design flows no longer supply correct predictability, forcing designers to either guardband their designs excessively or risk manufacturability problems. by modeling key manufacturing procedures in the implementation stream and optimizing early, designers reduce average turnaround time and increase their confidence that the chip will work as meant.

This 45-nm reference circulate is developed across the Cadence come across® platform for DFM-conscious prevention, detection and optimization. It has been proven within the typical Platform that points which can result in yield-limiting concerns in lithography are immediately and accurately recognized using the Cadence Litho physical Analyzer. These model-primarily based DFM consequences are used to force the Cadence SoC come across(TM) RTL-to-GDSII gadget -- for prevention and manufacturing-aware design closure, and Cadence Chip Optimizer -- for incremental area-primarily based interconnect optimization and final manufacturability optimization. Cadence QRC Extractor offers the primary modeling link between the physical, manufacturing and electrical domains. DFM consequences can also be extracted and timing affect will also be returned-annotated to the genuine implementation stage for correct mannequin-based timing optimization.

The Cadence 45nm reference movement for the general Platform, provides capabilities which aid carry manufacturing predictability back to the fashion designer. This drives effect in higher high-quality silicon with stronger time-to-extent.

"Low-vigor design and design for manufacturability are key components for purchasers when determining to undertake the 45-nm standard Platform know-how," pointed out Mark ireland, vice president, regular Platform, at IBM. "so as to address these issues, the average Platform businesses worked with Cadence engineers to convey this forty five-nm reference circulate. The outcomes is an ingenious yield-mindful answer with seamless implementation of energy intent using CPF."

"This collaboration between Cadence and the usual Platform gives a 45-nm silicon-aware reference circulation that can also be right now deployed by means of engineering groups looking for predictable design flows that bring superior nice of silicon," noted Chi-Ping Hsu, company vice president of Digital IC and vigour ahead at Cadence. "The combination of the Cadence Low-energy answer and DFM applied sciences, and the standard Platform 45-nm system expertise, supply designers a complete solution to handle the complexities and interdependent wants of low vigour and superior method know-how."

The advanced node capabilities within the Cadence 45nm Reference move supply "what you design is what you get" (WYDIWYG) modeling, superior low vigor ideas, and optimization of crucial manufacturing diversifications that may also be used to enrich results of the design part. This helps to influence in faster, lessen vigor and extra correct silicon.

Availability

The forty five-nanometer superior low-vigor, yield-optimization reference circulate might be purchasable in July by means of sending an electronic mail request to common_platform_45LP@cadence.com. This reference move kit carries a reference design, documentation and scripts to run the reference circulation.

About Cadence

Cadence makes it possible for global digital-design innovation and performs a necessary role within the advent of today's built-in circuits and electronics. purchasers use Cadence software and hardware, methodologies, and functions to design and check superior semiconductors, consumer electronics, networking and telecommunications device, and computing device methods. Cadence reported 2007 revenues of about $1.6 billion, and has about 5,100 personnel. The company is headquartered in San Jose, Calif., with earnings workplaces, design facilities, and analysis facilities around the globe to serve the international electronics business. more advice concerning the business, its products, and services is attainable at www.cadence.com.




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